ldrexh

Load Register Exclusive Halfword (Thumb)

LDREXH <Rt>, [<Rn>]

Loads halfword exclusively (Thumb).

Details

Loads a halfword from memory at the address in Rn into the low halfword of Rt (zero-extending to 32 bits) and opens the exclusive monitor for that address. The instruction does not modify the condition flags. Execution in Thumb-2 state only; typically paired with STREXH for atomic halfword operations.

Pseudocode Operation

address ← Rn
Rt ← ZeroExtend([address][15:0], 32)
SetExclusiveMonitor(address)

Example

LDREXH r3, [r1]

Encoding

Binary Layout
11101000110
1
Rn
Rt
1111
01
01
1111
 
Format Thumb Load Excl
Opcode 0xE8D00F5F
Extension A32 (Atomic)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01F00F9F LDREXH{<c>}{<q>} <Rt>, [<Rn>] A32 cond | 00011 | 11 | 1 | Rn | Rt | 1 | 1 | 1 | 1 | 1001 | 1111
0xE8D00F5F LDREXH{<c>}{<q>} <Rt>, [<Rn>] T32 11101000110 | 1 | Rn | Rt | 1111 | 01 | 01 | 1111

Description

Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    AArch32.SetExclusiveMonitors(address,2);
    R[t] = ZeroExtend(MemA[address,2], 32);