ldm

Load Multiple (Thumb)

LDM <Rn>!, <registers>

Load multiple registers (Thumb 16-bit).

Details

Load Multiple (Thumb 16-bit) loads multiple registers from memory at addresses formed by Rn, and optionally updates Rn to point to the next memory location. The register list is encoded in an 8-bit field. If Rn is the SP, this can function as a pop operation. Condition flags are not modified by the load itself, but if the PC is in the register list, execution continues at the loaded address.

Pseudocode Operation

address ← Rn
for each register in register_list (in ascending order):
  register ← [address]
  address ← address + 4
Rn ← address
if PC in register_list:
  PC ← loaded_PC_value

Example

LDM r1!, registers

Encoding

Binary Layout
1100
1
Rn
register_list
 
Format Thumb Load Multiple
Opcode 0xC800
Extension T32 (Base)

Operands

  • Rn
    First source / base general-purpose register
  • registers
    List

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x08900000 LDM{IA}{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 0 | 1 | 0 | W | 1 | Rn | register_list
0xC800 LDM{IA}{<c>}{<q>} <Rn>{!}, <registers> T32 1100 | 1 | Rn | register_list
0xE8900000 LDM{IA}{<c>}.W <Rn>{!}, <registers> T32 1110100 | 01 | 0 | W | 1 | Rn | P | M | register_list
0x08508000 LDM{<amode>}{<c>}{<q>} <Rn>{!}, <registers_with_pc>^ A32 cond | 100 | P | U | 1 | W | 1 | Rn | 1 | register_list
0x08500000 LDM{<amode>}{<c>}{<q>} <Rn>, <registers_without_pc>^ A32 cond | 100 | P | U | 1 | 0 | 1 | Rn | 0 | register_list
0x08100000 LDMDA{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 0 | 0 | 0 | W | 1 | Rn | register_list
0x09100000 LDMDB{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 1 | 0 | 0 | W | 1 | Rn | register_list
0xE9100000 LDMDB{<c>}{<q>} <Rn>{!}, <registers> T32 1110100 | 10 | 0 | W | 1 | Rn | P | M | register_list
0x09900000 LDMIB{<c>}{<q>} <Rn>{!}, <registers> A32 cond | 100 | 1 | 1 | 0 | W | 1 | Rn | register_list

Description

Load Multiple (Increment After, Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC. Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Related system instructions are LDM (User registers) and LDM (exception return).

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n];
    for i = 0 to 14
        if registers<i> == '1' then
            R[i] = MemS[address,4];  address = address + 4;
    if registers<15> == '1' then
        LoadWritePC(MemS[address,4]);
    if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
    if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;