smull

Signed Multiply Long (Thumb)

SMULL <RdLo>, <RdHi>, <Rn>, <Rm>

Signed Multiply (64-bit result).

Details

Multiply Rn by Rm as signed 32-bit values and place the 64-bit result in RdHi:RdLo, where RdHi receives the upper 32 bits and RdLo receives the lower 32 bits. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

Pseudocode Operation

result ← SignedMultiply(Rn, Rm); RdHi ← result[63:32]; RdLo ← result[31:0]

Example

SMULL r1, r0, r1, r2

Encoding

Binary Layout
111110111
000
Rn
RdLo
RdHi
0000
Rm
 
Format Thumb Mul
Opcode 0xFB800000
Extension A32 (Base)

Operands

  • RdLo
    Low
  • RdHi
    High
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x00C00090 SMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> A32 cond | 0000 | 110 | 0 | RdHi | RdLo | Rm | 1001 | Rn
0xFB800000 SMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm> T32 111110111 | 000 | Rn | RdLo | RdHi | 0000 | Rm

Description

Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = SInt(R[n]) * SInt(R[m]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;
    if setflags then
        PSTATE.N = result<63>;
        PSTATE.Z = IsZeroBit(result<63:0>);
        // PSTATE.C, PSTATE.V unchanged