at

Address Translate (Stage 1 Write)

AT S1E1W, <Xt>

Performs stage 1 address translation for write permission.

Details

Performs stage 1 address translation for a virtual address in the current execution level, treating the access as a write. The translation result (physical address and attributes) is written to the PAR_EL1 register. No condition flags are affected. This is an AArch64-only instruction that requires appropriate privilege level to access the address translation system registers.

Pseudocode Operation

address ← Xt
translation_result ← TranslateAddress(address, S1E1W, current_EL)
PAR_EL1 ← translation_result

Example

AT S1E1W, x3

Encoding

Binary Layout
1101010100
0
01
op1
0111
CRm
op2
Rt
 
Format System
Opcode 0xD5087800
Extension Base (System)

Operands

  • op
    S1E1W
  • Xt
    Virt Addr

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xD5087800 AT <at_op>, <Xt> A64 1101010100 | 0 | 01 | op1 | 0111 | CRm | op2 | Rt

Description

Address Translate. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.