rsb.w

Reverse Subtract (Wide)

RSB.W <Rd>, <Rn>, <Operand2>

Thumb-2 32-bit reverse subtract.

Pseudocode Operation

result ← Operand2 - Rn; Rd ← result; if S == 1 then: N ← result[31]; Z ← (result == 0); C ← NOT BorrowFrom(Operand2, Rn); V ← OverflowFrom(Operand2, -Rn);

Example

RSB.W r0, r1, r2

Encoding

Binary Layout

1110101

31:25

1110

24:21

19:16

imm3

14:12

11:8

imm2

7:6

stype

5:4

3:0

Format Thumb2 Data Proc

Opcode 0xEBC00000

Extension T32 (Thumb2)

Operands

Rd
Destination general-purpose register
Rn
First source / base general-purpose register
Operand2
Flexible second operand (register or shifted register)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x02600000	RSB{<c>}{<q>} {<Rd>,} <Rn>, #<const>	A32	cond \| 0010 \| 011 \| 0 \| Rn \| Rd \| imm12
0x4240	RSB<c>{<q>} {<Rd>, }<Rn>, #0	T32	010000 \| 1001 \| Rn \| Rd
0xF1C00000	RSB<c>.W {<Rd>,} <Rn>, #0	T32	11110 \| i \| 0 \| 1110 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm8
0x00600060	RSB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	A32	cond \| 0000 \| 011 \| 0 \| Rn \| Rd \| 00000 \| 11 \| 0 \| Rm
0x00600000	RSB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}	A32	cond \| 0000 \| 011 \| 0 \| Rn \| Rd \| imm5 \| stype \| 0 \| Rm
0xEBC00030	RSB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, RRX	T32	1110101 \| 1110 \| 0 \| Rn \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEBC00000	RSB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, <shift> #<amount>}	T32	1110101 \| 1110 \| 0 \| Rn \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x00600010	RSB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs>	A32	cond \| 0000 \| 011 \| 0 \| Rn \| Rd \| Rs \| 0 \| stype \| 1 \| Rm

Description

Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. If the destination register is not the PC, the RSBS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    shifted = Shift(R[m], shift_t, shift_n, PSTATE.C);
    (result, nzcv) = AddWithCarry(NOT(R[n]), shifted, '1');
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;