fcvtnu

Floating-Point Convert to Unsigned Integer (Nearest, ties to Even)

FCVTNU <Wd|Xd>, <Hn|Sn|Dn>

Converts float to unsigned integer, rounding to nearest (bankers' round).

Details

Converts a scalar floating-point value to an unsigned integer, rounding to nearest with ties to even (bankers' round). Sets condition flags based on the integer result. Raises Invalid Operation exception on overflow or invalid input. AArch64-only instruction.

Pseudocode Operation

operand ← Vn
intval ← RoundTowardNearestEven(operand)
if intval > MaxUInt(destination_width) or intval < 0 then
  GenerateException(InvalidOperation)
else
  Rd ← ZeroExtend(intval)
  UpdateFlags(intval)
end

Example

FCVTNU Wd, Dn

Encoding

Binary Layout
0
0
0
11110
00
1
00
001
000000
Rn
Rd
 
Format FP Conversion
Opcode 0x1E210000
Extension Floating Point

Operands

  • Rd
    Int Dest
  • Vn
    Float Src

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7E79A800 FCVTNU <Hd>, <Hn> A64 01 | 1 | 11110 | 0 | 1111001101 | 0 | 10 | Rn | Rd
0x7E21A800 FCVTNU <V><d>, <V><n> A64 01 | 1 | 11110 | 0 | sz | 100001101 | 0 | 10 | Rn | Rd
0x2E79A800 FCVTNU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | 1111001101 | 0 | 10 | Rn | Rd
0x2E21A800 FCVTNU <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | sz | 100001101 | 0 | 10 | Rn | Rd
0x1EE10000 FCVTNU <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 001 | 000000 | Rn | Rd
0x9EE10000 FCVTNU <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 00 | 001 | 000000 | Rn | Rd
0x1E210000 FCVTNU <Wd>, <Sn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 001 | 000000 | Rn | Rd
0x9E210000 FCVTNU <Xd>, <Sn> A64 1 | 0 | 0 | 11110 | 00 | 1 | 00 | 001 | 000000 | Rn | Rd
0x1E610000 FCVTNU <Wd>, <Dn> A64 0 | 0 | 0 | 11110 | 01 | 1 | 00 | 001 | 000000 | Rn | Rd
0x9E610000 FCVTNU <Xd>, <Dn> A64 1 | 0 | 0 | 11110 | 01 | 1 | 00 | 001 | 000000 | Rn | Rd

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, TRUE, FPCR, rounding, intsize);
X[d, intsize] = intval;