vld1

Vector Load Multiple (Single Element)

VLD1<c>.<size> <list>, [<Rn>]{!}

Loads vector data from memory (interleaved or sequential).

Pseudocode Operation

address ← Rn
for each register in list
  load vector from address
  address ← address + stride
if writeback
  Rn ← Rn + total_bytes_loaded

Example

VLD1.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
31:23
D
22
1
21
0
20
Rn
19:16
Vd
15:12
00
11:10
00
9:8
index_align
7:4
1101
3:0
 
Format NEON Load
Opcode 0xF4A0000D
Extension NEON (SIMD)

Operands

  • list
    Dest Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF4A0000F VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1111
0xF4A0000D VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1101
0xF4A00000 VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | Rm
0xF4A0040F VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 00 | index_align | 1111
0xF4A0040D VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 00 | index_align | 1101
0xF4A00400 VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 01 | 00 | index_align | Rm
0xF4A0080F VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 00 | index_align | 1111
0xF4A0080D VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 00 | index_align | 1101
0xF4A00800 VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 1 | 0 | Rn | Vd | 10 | 00 | index_align | Rm
0xF9A0000F VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1111
0xF9A0000D VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | 1101
0xF9A00000 VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> T32 111110011 | D | 1 | 0 | Rn | Vd | 00 | 00 | index_align | Rm
0xF9A0040F VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 00 | index_align | 1111
0xF9A0040D VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 1 | 0 | Rn | Vd | 01 | 00 | index_align | 1101

Description

Load single 1-element structure to one lane of one register loads one element from memory into one element of a register. Elements of the register that are not loaded are unchanged. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckAdvSIMDEnabled();

    address = R[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked);
    if !IsAligned(address, alignment) then
        AArch32.Abort(address, AlignmentFault(accdesc));

    Elem[D[d],index,8*ebytes] = MemU[address,ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + ebytes;