decw

SVE Decrement Scalar by Word Count

DECW <Xdn>, <pattern> {, MUL #<imm>}

Decrements a register by the number of active words.

Details

Decrements a 64-bit scalar register by the count of active words in the SVE vector length, optionally multiplied by an immediate. The decrement amount is calculated as VL/4 (number of 32-bit elements) times an optional multiplier (1-16). No condition flags are affected. AArch64-only instruction requiring SVE extension.

Pseudocode Operation

count ← CountActiveWords(pattern)
multiplier ← imm4 if imm4 != 0 else 1
Xdn ← Xdn - (count * multiplier)

Example

DECW Xdn, pattern

Encoding

Binary Layout
00000100
1
0
11
imm4
11100
1
pattern
Rdn
 
Format SVE Inc/Dec
Opcode 0x04B0E400
Extension SVE

Operands

  • Xdn
    Register
  • pattern
    Predicate Pattern

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04B0E400 DECW <Xdn>{, <pattern>{, MUL #<imm>}} A64 00000100 | 1 | 0 | 11 | imm4 | 11100 | 1 | pattern | Rdn
0x04B0C400 DECW <Zdn>.S{, <pattern>{, MUL #<imm>}} A64 00000100 | 1 | 0 | 11 | imm4 | 11000 | 1 | pattern | Zdn

Description

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement the scalar destination. The named predicate constraint limits the number of active elements in a single predicate to: Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

Operation

CheckSVEEnabled();
integer count = DecodePredCount(pat, esize);
constant integer VL = CurrentVL;
bits(64) operand1 = X[dn, 64];

X[dn, 64] = operand1 - (count * imm);