ins

Insert Vector Element (General)

INS <Vd>.<Ts>[<index>], <Rn>

Moves data from a GPR to a specific vector element.

Details

Moves a single 64-bit value from a general-purpose register to a specified element position within a vector register, leaving other elements unchanged. The destination element index is encoded in the imm5 field, with the element size implicitly 64-bit. This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

Pseudocode Operation

element_index ← decode_index_from_imm5(imm5);
Vd.D[element_index] ← Rn;

Example

INS v0.4s.Ts[index], r1

Encoding

Binary Layout
0
1
0
01110000
imm5
0
0011
1
Rn
Rd
 
Format SIMD Copy
Opcode 0x4E001C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • index
    Index
  • Rn
    Src GPR

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6E000400 INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>] A64 0 | 1 | 1 | 01110000 | imm5 | 0 | imm4 | 1 | Rn | Rd
0x4E001C00 INS <Vd>.<Ts>[<index>], <R><n> A64 0 | 1 | 0 | 01110000 | imm5 | 0 | 0011 | 1 | Rn | Rd

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register. This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(esize) element = X[n, esize];
bits(128) result;

result = V[d, 128];
Elem[result, index, esize] = element;
V[d, 128] = result;