lsr

SVE Logical Shift Right (Predicated)

LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Shifts elements right logically under predicate.

Details

Performs element-wise logical shift right on SVE vector elements under predicate control, where the shift amount for each element comes from the corresponding element of Zm. Shifted-in bits are zeros. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

Pseudocode Operation

for i = 0 to VL/esize-1 do
  if Pg[i] then
    shift_amount ← Zm[i*esize +: esize] AND (esize*8-1)
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] >> shift_amount
  else
    // element unchanged
endfor

Example

LSR z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
00000100
size
010
0
0
1
100
Pg
Zm
Zdn
 
Format SVE Shift
Opcode 0x04118000
Extension SVE

Operands

  • Zdn
    Dest/Src
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1AC02400 LSR <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 0010 | 01 | Rn | Rd
0x9AC02400 LSR <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 0010 | 01 | Rn | Rd
0x53007C00 LSR <Wd>, <Wn>, #<shift> A64 0 | 10 | 100110 | 0 | immr | 011111 | Rn | Rd
0xD340FC00 LSR <Xd>, <Xn>, #<shift> A64 1 | 10 | 100110 | 1 | immr | 111111 | Rn | Rd
0x04018000 LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> A64 00000100 | tszh | 00 | 0 | 0 | 0 | 1 | 100 | Pg | tszl | imm3 | Zdn
0x04198000 LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D A64 00000100 | size | 011 | 0 | 0 | 1 | 100 | Pg | Zm | Zdn
0x04118000 LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 010 | 0 | 0 | 1 | 100 | Pg | Zm | Zdn
0x04209400 LSR <Zd>.<T>, <Zn>.<T>, #<const> A64 00000100 | tszh | 1 | tszl | imm3 | 1001 | 0 | 1 | Zn | Zd
0x04208400 LSR <Zd>.<T>, <Zn>.<T>, <Zm>.D A64 00000100 | size | 1 | Zm | 1000 | 0 | 1 | Zn | Zd

Description

Shift right, inserting zeroes, active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element1 = Elem[operand1, e, esize];
        bits(esize) element2 = Elem[operand2, e, esize];
        integer shift = Min(UInt(element2), esize);
        Elem[result, e, esize] = LSR(element1, shift);
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;