ldp

Load Pair SIMD&FP Registers

LDP <St1|Dt1|Qt1>, <St2|Dt2|Qt2>, [<Xn|SP>, #<imm>]

Loads two floating-point/SIMD registers.

Pseudocode Operation

address ← (Xn | SP) + (imm7 << scale); Vt1 ← [address]; Vt2 ← [address + operand_size]

Example

LDP Qt1, Qt2, [x1, #16]

Encoding

Binary Layout

00

31:30

101

29:27

1

26

010

25:23

1

22

imm7

21:15

Rt2

14:10

Rn

9:5

Rt

4:0

 

Format Load/Store Pair

Opcode 0x2D400000

Extension Floating Point

Operands

• St1|Dt1|Qt1
  First transfer SIMD&FP register (single, double or quad-precision)
• St2|Dt2|Qt2
  Second transfer SIMD&FP register (single, double or quad-precision)
• Xn|SP
  First source / base 64-bit integer register
• imm
  Signed immediate value

Related

Other forms of ldp

• ldp Load Pair of Registers
• ldp Load Pair of Registers (64-bit)

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2CC00000	LDP <St1>, <St2>, [<Xn|SP>], #<imm>		A64		00 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x6CC00000	LDP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>		A64		01 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0xACC00000	LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>		A64		10 | 101 | 1 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x2DC00000	LDP <St1>, <St2>, [<Xn|SP>, #<imm>]!		A64		00 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x6DC00000	LDP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!		A64		01 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0xADC00000	LDP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!		A64		10 | 101 | 1 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x2D400000	LDP <St1>, <St2>, [<Xn|SP>{, #<imm>}]		A64		00 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0x6D400000	LDP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]		A64		01 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0xAD400000	LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]		A64		10 | 101 | 1 | 010 | 1 | imm7 | Rt2 | Rn | Rt
0x28C00000	LDP <Wt1>, <Wt2>, [<Xn|SP>], #<imm>		A64		00 | 101 | 0 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0xA8C00000	LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>		A64		10 | 101 | 0 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x29C00000	LDP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!		A64		00 | 101 | 0 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0xA9C00000	LDP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!		A64		10 | 101 | 0 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x29400000	LDP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]		A64		00 | 101 | 0 | 010 | 1 | imm7 | Rt2 | Rn | Rt

Description

Load Pair of SIMD&FP registers. This instruction loads a pair of SIMD&FP registers from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();
bits(64) address;
bits(64) address2;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;

AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, FALSE, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

address2 = GenerateAddress(address, dbytes, accdesc);
data1 = Mem[address, dbytes, accdesc];
data2 = Mem[address2, dbytes, accdesc];
if rt_unknown then
    data1 = bits(datasize) UNKNOWN;
    data2 = bits(datasize) UNKNOWN;
V[t, datasize] = data1;
V[t2, datasize] = data2;

if wback then
    if postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;