uqsub16

Unsigned Saturating Subtract 16

UQSUB16<c> <Rd>, <Rn>, <Rm>

Unsigned saturating subtract of 2 halfwords.

Pseudocode Operation

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
diff1 ← half1_rn - half1_rm; diff2 ← half2_rn - half2_rm
Rd[15:0] ← (diff1 < 0) ? 0 : diff1
Rd[31:16] ← (diff2 < 0) ? 0 : diff2

Example

UQSUB16 r0, r1, r2

Encoding

Binary Layout

cond

31:28

01100

27:23

110

22:20

Rn

19:16

Rd

15:12

1

11

1

10

1

9

1

8

0

7

11

6:5

1

4

Rm

3:0

 

Format SIMD Integer

Opcode 0x06600F70

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x06600F70	UQSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 01100 | 110 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 11 | 1 | Rm
0xFAD0F050	UQSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110101 | 101 | Rn | 1111 | Rd | 0 | 1 | 0 | 1 | Rm

Description

Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 <= x <= 216 - 1, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
    diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
    R[d]<15:0>  = UnsignedSat(diff1, 16);
    R[d]<31:16> = UnsignedSat(diff2, 16);