uxtah

Unsigned Extend and Add Halfword

UXTAH<c> <Rd>, <Rn>, <Rm> {, <rotation>}

Zero-extends a halfword and adds to Rn.

Details

Zero-extends a halfword (16-bit) from Rm, optionally rotates it by 0, 8, 16, or 24 bits, and adds the result to Rn, storing the sum in Rd. The instruction executes conditionally based on the condition code and does not update the condition flags. This is an A32 DSP extension instruction.

Pseudocode Operation

rotated ← ROR(Rm, rotation)
extended ← ZeroExtend(rotated[15:0], 32)
Rd ← Rn + extended

Example

UXTAH r0, r1, r2

Encoding

Binary Layout
cond
01101
1
11
Rn
Rd
rotate
0
0
0111
Rm
 
Format Data Proc
Opcode 0x06F00070
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    Accumulator
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06F00070 UXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>} A32 cond | 01101 | 1 | 11 | Rn | Rd | rotate | 0 | 0 | 0111 | Rm
0xFA10F080 UXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>} T32 111110100 | 00 | 1 | Rn | 1111 | Rd | 1 | 0 | rotate | Rm

Description

Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = R[n] + ZeroExtend(rotated<15:0>, 32);