qadd

Saturating Add (A32)

QADD<c> <Rd>, <Rm>, <Rn>

Adds two values and saturates the result.

Details

Adds Rm to Rn and saturates the result; the saturated sum is placed in Rd. If overflow occurs (signed arithmetic), the result is saturated to 0x7FFFFFFF (positive overflow) or 0x80000000 (negative overflow). This instruction is A32-only, is conditional (respects condition code suffix), and does not affect condition flags. Requires ARMv5TE or later.

Pseudocode Operation

result ← Rn + Rm; if SignedOverflow(result) then Rd ← Saturate(result) else Rd ← result

Example

QADD r0, r2, r1

Encoding

Binary Layout
cond
00010
00
0
Rn
Rd
0
0
0
0
0101
Rm
 
Format Data Proc
Opcode 0x01000050
Extension A32 (Sat)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x01000050 QADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn> A32 cond | 00010 | 00 | 0 | Rn | Rd | 0 | 0 | 0 | 0 | 0101 | Rm
0xFA80F080 QADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn> T32 111110101 | 000 | Rn | 1111 | Rd | 10 | 00 | Rm

Description

Saturating Add adds two register values, saturates the result to the 32-bit signed integer range -231 to (231 - 1), and writes the result to the destination register. If saturation occurs, it sets PSTATE.Q to 1.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    boolean sat;
    (R[d], sat) = SignedSatQ(SInt(R[m]) + SInt(R[n]), 32);
    if sat then
        PSTATE.Q = '1';