vpmin

Vector Pairwise Minimum

VPMIN<c>.<dt> <Dd>, <Dn>, <Dm>

Minimum of adjacent pairs.

Details

Computes the minimum of adjacent pairs of elements from the source operands and places the results in the destination register, reducing dimensionality by half. For each pair, the smaller element is selected. No condition flags are affected. Execution is available in both A32 and T32 instruction sets via NEON.

Pseudocode Operation

case dt of
  when I8:  for i = 0 to 3: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])
  when I16: for i = 0 to 1: Dd[i] ← min(Dn[2*i], Dn[2*i+1], Dm[2*i], Dm[2*i+1])
  when I32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])
  when F32: Dd[0] ← min(Dn[0], Dn[1]); Dd[1] ← min(Dm[0], Dm[1])

Example

VPMIN.dt d0, d1, d2

Encoding

Binary Layout
1111001
U
0
D
size
Vn
Vd
1010
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000A10
Extension NEON (SIMD)

Operands

  • Dd
    Destination 64-bit SIMD/FP register
  • Dn
    First source 64-bit SIMD/FP register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3200F00 VPMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xFF200F00 VPMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 1 | sz | Vn | Vd | 1111 | N | 0 | M | 0 | Vm
0xF2000A10 VPMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | U | 0 | D | size | Vn | Vd | 1010 | N | 0 | M | 1 | Vm
0xEF000A10 VPMIN{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | U | 11110 | D | size | Vn | Vd | 1010 | N | 0 | M | 1 | Vm

Description

Vector Pairwise Minimum compares adjacent pairs of elements in two doubleword vectors, and copies the smaller of each pair into the corresponding element in the destination doubleword vector. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    bits(64) dest;
    h = elements DIV 2;

    for e = 0 to h-1
        op1 = Int(Elem[D[n],2*e,esize], unsigned);
        op2 = Int(Elem[D[n],2*e+1,esize], unsigned);
        result = if maximum then Max(op1,op2) else Min(op1,op2);
        Elem[dest,e,esize] = result<esize-1:0>;
        op1 = Int(Elem[D[m],2*e,esize], unsigned);
        op2 = Int(Elem[D[m],2*e+1,esize], unsigned);
        result = if maximum then Max(op1,op2) else Min(op1,op2);
        Elem[dest,e+h,esize] = result<esize-1:0>;

    D[d] = dest;