fcvtzs
Floating-point Convert to Signed Integer (Round towards Zero)
FCVTZS <Xd>, <Dn>
Converts floating-point to signed integer.
Details
Converts a 64-bit double-precision floating-point value in Dn to a signed 64-bit integer, rounding towards zero, and stores the result in Xd. If the result overflows the signed 64-bit range, the result is the most negative or most positive 64-bit integer depending on the input sign. The condition flags NZCV are not affected. This is an AArch64-only instruction requiring the Floating-Point extension.
Pseudocode Operation
Xd ← ConvertToSignedInteger(Dn, RoundTowardZero)
if (overflow) then
Xd ← (Dn < 0) ? INT64_MIN : INT64_MAXExample
FCVTZS x0, d1
Encoding
Binary Layout
1
0
0
11110
00
1
11
000
000000
Rn
Rd
Operands
-
Xd
Dest (Int64) -
Dn
Src (Double)
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x5F00FC00 | FCVTZS <V><d>, <V><n>, #<fbits> | A64 | 01 | 0 | 111110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x0F00FC00 | FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits> | A64 | 0 | Q | 0 | 011110 | immh | immb | 11111 | 1 | Rn | Rd | ||
| 0x5EF9B800 | FCVTZS <Hd>, <Hn> | A64 | 01 | 0 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x5EA1B800 | FCVTZS <V><d>, <V><n> | A64 | 01 | 0 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x0EF9B800 | FCVTZS <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd | ||
| 0x0EA1B800 | FCVTZS <Vd>.<T>, <Vn>.<T> | A64 | 0 | Q | 0 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd | ||
| 0x1ED80000 | FCVTZS <Wd>, <Hn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9ED80000 | FCVTZS <Xd>, <Hn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1E180000 | FCVTZS <Wd>, <Sn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9E180000 | FCVTZS <Xd>, <Sn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1E580000 | FCVTZS <Wd>, <Dn>, #<fbits> | A64 | 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x9E580000 | FCVTZS <Xd>, <Dn>, #<fbits> | A64 | 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd | ||
| 0x1EF80000 | FCVTZS <Wd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd | ||
| 0x9EF80000 | FCVTZS <Xd>, <Hn> | A64 | 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd |
Description
Floating-point Convert to Signed integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register.
A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPEnabled64(); bits(decode_fltsize) fltval; bits(intsize) intval; fltval = V[n, decode_fltsize]; intval = FPToFixed(fltval, 0, FALSE, FPCR, rounding, intsize); X[d, intsize] = intval;