asr
Arithmetic Shift Right (Immediate 64-bit)
ASR <Xd>, <Xn>, #<shift>
Arithmetic shift right by immediate (64-bit).
Details
Performs an arithmetic right shift of Xn by an immediate amount, storing the result in Xd. The sign bit (bit 63) is replicated into vacated bit positions. No condition flags are affected.
Pseudocode Operation
Xd ← Xn >> shift (arithmetic, sign-extended)Example
ASR x0, x1, #LSL
Encoding
Binary Layout
1
00
100110
1
immr
111111
Rn
Rd
Operands
-
Xd
Destination 64-bit integer register -
Xn
First source / base 64-bit integer register -
shift
Shift amount
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x1AC02800 | ASR <Wd>, <Wn>, <Wm> | A64 | 0 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd | ||
| 0x9AC02800 | ASR <Xd>, <Xn>, <Xm> | A64 | 1 | 0 | 0 | 11010110 | Rm | 0010 | 10 | Rn | Rd | ||
| 0x13007C00 | ASR <Wd>, <Wn>, #<shift> | A64 | 0 | 00 | 100110 | 0 | immr | 011111 | Rn | Rd | ||
| 0x9340FC00 | ASR <Xd>, <Xn>, #<shift> | A64 | 1 | 00 | 100110 | 1 | immr | 111111 | Rn | Rd | ||
| 0x04008000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const> | A64 | 00000100 | tszh | 00 | 0 | 0 | 0 | 0 | 100 | Pg | tszl | imm3 | Zdn | ||
| 0x04188000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D | A64 | 00000100 | size | 011 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x04108000 | ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 00000100 | size | 010 | 0 | 0 | 0 | 100 | Pg | Zm | Zdn | ||
| 0x04209000 | ASR <Zd>.<T>, <Zn>.<T>, #<const> | A64 | 00000100 | tszh | 1 | tszl | imm3 | 1001 | 0 | 0 | Zn | Zd | ||
| 0x04208000 | ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D | A64 | 00000100 | size | 1 | Zm | 1000 | 0 | 0 | Zn | Zd |
Description
Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of the sign bit in the upper bits and zeros in the lower bits, and writes the result to the destination register.