asr

Arithmetic Shift Right (Immediate 64-bit)

ASR <Xd>, <Xn>, #<shift>

Arithmetic shift right by immediate (64-bit).

Pseudocode Operation

Xd ← Xn >> shift (arithmetic, sign-extended)

Example

ASR x0, x1, #LSL

Encoding

Binary Layout

30:29

100110

28:23

immr

21:16

111111

15:10

9:5

4:0

Format Data Processing (Immediate)

Opcode 0x9340FC00

Extension Base

Operands

Xd
Destination 64-bit integer register
Xn
First source / base 64-bit integer register
shift
Shift amount

Other forms of asr

asr Arithmetic Shift Right (Immediate)
asr Arithmetic Shift Right (Register)
asr Arithmetic Shift Right (Register 64-bit)
asr SVE Arithmetic Shift Right (Predicated)
asr Arithmetic Shift Right (A32)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x1AC02800	ASR <Wd>, <Wn>, <Wm>	A64	0 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 10 \| Rn \| Rd
0x9AC02800	ASR <Xd>, <Xn>, <Xm>	A64	1 \| 0 \| 0 \| 11010110 \| Rm \| 0010 \| 10 \| Rn \| Rd
0x13007C00	ASR <Wd>, <Wn>, #<shift>	A64	0 \| 00 \| 100110 \| 0 \| immr \| 011111 \| Rn \| Rd
0x9340FC00	ASR <Xd>, <Xn>, #<shift>	A64	1 \| 00 \| 100110 \| 1 \| immr \| 111111 \| Rn \| Rd
0x04008000	ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>	A64	00000100 \| tszh \| 00 \| 0 \| 0 \| 0 \| 0 \| 100 \| Pg \| tszl \| imm3 \| Zdn
0x04188000	ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D	A64	00000100 \| size \| 011 \| 0 \| 0 \| 0 \| 100 \| Pg \| Zm \| Zdn
0x04108000	ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>	A64	00000100 \| size \| 010 \| 0 \| 0 \| 0 \| 100 \| Pg \| Zm \| Zdn
0x04209000	ASR <Zd>.<T>, <Zn>.<T>, #<const>	A64	00000100 \| tszh \| 1 \| tszl \| imm3 \| 1001 \| 0 \| 0 \| Zn \| Zd
0x04208000	ASR <Zd>.<T>, <Zn>.<T>, <Zm>.D	A64	00000100 \| size \| 1 \| Zm \| 1000 \| 0 \| 0 \| Zn \| Zd

Description

Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of the sign bit in the upper bits and zeros in the lower bits, and writes the result to the destination register.

asr