ushr

Vector Unsigned Shift Right

USHR <Vd>.<T>, <Vn>.<T>, #<shift>

Shifts elements right (logical).

Details

Vector Unsigned Shift Right performs a logical right shift on each element of a NEON register by an immediate value, filling vacated bit positions with zeros. The immediate shift amount is encoded in the imm field and must be within the range [1, element_width]; shifting by the element width or more produces a zero result. This instruction does not modify the condition flags. AArch64-only NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  if shift_amount <= element_width(size) then
    Vd[i] ← Vn[i] >> shift_amount
  else
    Vd[i] ← 0
  end if
end for

Example

USHR v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout
0
Q
1
011110
immh
immb
00
0
0
01
Rn
Rd
 
Format SIMD Shift Imm
Opcode 0x2F000400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • shift
    Imm

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7F400400 USHR D<d>, D<n>, #<shift> A64 01 | 1 | 111110 | immh | immb | 00 | 0 | 0 | 01 | Rn | Rd
0x2F000400 USHR <Vd>.<T>, <Vn>.<T>, #<shift> A64 0 | Q | 1 | 011110 | immh | immb | 00 | 0 | 0 | 01 | Rn | Rd

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) operand2;
bits(datasize) result;
integer element;

operand2 = if accumulate then V[d, datasize] else Zeros(datasize);
for e = 0 to elements-1
    element = RShr(Int(Elem[operand, e, esize], unsigned), shift, round);
    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

V[d, datasize] = result;