ands

Bitwise AND and Set Flags (Shifted Register)

ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise AND shifted register, updates flags.

Details

The Bitwise AND and Set Flags instruction bitwise AND shifted register, updates flags.

Pseudocode Operation

Wd ← Wn AND Wm

Example

ANDS w0, w1, w2

Encoding

Binary Layout
01101010
00
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x6A000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register