ands

Bitwise AND and Set Flags (Shifted Register)

ANDS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Bitwise AND shifted register, updates flags.

Details

Performs a bitwise AND between Wn and a shifted Wm, storing the result in Wd and updating the condition flags. Sets the Z flag if the result is zero, the N flag based on bit 31 of the result, and clears the C and V flags.

Pseudocode Operation

result ← Wn AND (Wm shifted by shift_amount)
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0

Example

ANDS w0, w1, w2

Encoding

Binary Layout
0
11
01010
shift
0
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x6A000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x72000000 ANDS <Wd>, <Wn>, #<imm> A64 0 | 11 | 100100 | 0 | immr | imms | Rn | Rd
0xF2000000 ANDS <Xd>, <Xn>, #<imm> A64 1 | 11 | 100100 | N | immr | imms | Rn | Rd
0x6A000000 ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0xEA000000 ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 11 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25404000 ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 1 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd

Description

Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;


result = operand1 AND operand2;
PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00';

X[d, datasize] = result;