fjcvtzs

Floating-Point Javascript Convert

FJCVTZS <Wd>, <Dn>

Converts double to signed 32-bit integer with JS rounding semantics.

Pseudocode Operation

if IsNaN(Dn) or (Dn > 2^31 - 1) or (Dn < -2^31) then Wd ← 0; C ← 1; else Wd ← SignedSaturate(RoundTowardZero(Dn), 32); C ← 0;

Example

FJCVTZS w0, d1

Encoding

Binary Layout

11110

28:24

23:22

20:19

110

18:16

000000

15:10

9:5

4:0

Format Float Convert

Opcode 0x1E7E0000

Extension FEAT_JSCVT

Operands

Wd
Destination 32-bit integer register
Dn
First source 64-bit SIMD/FP register

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x1E7E0000	FJCVTZS <Wd>, <Dn>		A64		0 \| 0 \| 0 \| 11110 \| 01 \| 1 \| 11 \| 110 \| 000000 \| Rn \| Rd

Description

Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be represented as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(64) fltval;
bits(32) intval;

bit z;
fltval = V[n, 64];
(intval, z) = FPToFixedJS(fltval, FPCR, 32);
PSTATE.<N,Z,C,V> = '0':z:'00';
X[d, 32] = intval;