fmla

SVE Floating-Point Fused Multiply-Add

FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>

Calculates (Zda + Zn * Zm) under predicate.

Details

The SVE Floating-Point Fused Multiply-Add instruction calculates (Zda + Zn * Zm) under predicate.

Pseudocode Operation

Zda ← Pg + Zn
// Flags affected: N, Z, C, V

Example

FMLA z0.s.T, p0/m/M, z1.s.T, z2.s.T

Encoding

Binary Layout
01100101
00
1
00000
Pg
Zm
Zn
Zda
 
Format SVE FP Ternary
Opcode 0x65200000
Extension SVE

Operands

  • Zda
    Dest/Addend
  • Pg
    Mask
  • Zn
    First source scalable vector register (SVE)
  • Zm
    Second source scalable vector register (SVE)