vbif

Vector Bit Insert False

VBIF<c> <Qd>, <Qm>, <Qn>

Inserts bits from Vm into Vd where Vn (mask) is 0.

Pseudocode Operation

for i = 0 to 127
  if Qn[i] == 0 then Qd[i] ← Qm[i]

Example

VBIF q0, q2, q1

Encoding

Binary Layout

1111001

31:25

1

24

0

23

D

22

11

21:20

Vn

19:16

Vd

15:12

0001

11:8

N

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF3300110

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register
• Qn
  Mask

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3300110	VBIF{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		A32		1111001 | 1 | 0 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF3300150	VBIF{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		A32		1111001 | 1 | 0 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xFF300110	VBIF{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>		T32		111 | 1 | 11110 | D | 11 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xFF300150	VBIF{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>		T32		111 | 1 | 11110 | D | 11 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Bitwise Insert if False inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 0, otherwise leaves the bit in the destination register unchanged. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        case operation of
            when VBitOps_VBIF  D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]));
            when VBitOps_VBIT  D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]));
            when VBitOps_VBSL  D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));