usubl

Unsigned Subtract Long

USUBL <Vd>.<Td>, <Vn>.<Ts>, <Vm>.<Ts>

Subtracts unsigned narrow vectors, producing wider result.

Details

Subtracts corresponding unsigned elements of two narrow SIMD vectors and places the results in a wider vector, zero-extending intermediate products. This is an AArch64-only NEON instruction that operates on integer element types (8, 16, or 32 bits) and produces results twice the width. Condition flags are not affected.

Pseudocode Operation

for i = 0 to (128 >> (size+1)) - 1 do
  op1 ← ZeroExtend(Vn[i], element_width)
  op2 ← ZeroExtend(Vm[i], element_width)
  Vd[i] ← op1 - op2
end for

Example

USUBL v0.4s.Td, v1.4s.Ts, v2.4s.Ts

Encoding

Binary Layout
0
Q
1
01110
size
1
Rm
00
1
000
Rn
Rd
 
Format SIMD Three Register Diff
Opcode 0x2E202000
Extension NEON (SIMD)

Operands

  • Vd
    Dest (Wide)
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E202000 USUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 00 | 1 | 000 | Rn | Rd

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements. The USUBL instruction extracts each source vector from the lower half of each source register. The USUBL2 instruction extracts each source vector from the upper half of each source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part, datasize];
bits(datasize) operand2 = Vpart[m, part, datasize];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d, 2*datasize] = result;