vtrn

Vector Transpose

VTRN<c>.<dt> <Qd>, <Qm>

Transposes elements of two vectors.

Pseudocode Operation

temp_d ← Qd
temp_m ← Qm
for i ← 0 to (128 / element_width) - 1:
  if i is even:
    Qd[i * element_width +: element_width] ← temp_d[i * element_width +: element_width]
    Qm[i * element_width +: element_width] ← temp_m[i * element_width +: element_width]
  else:
    Qd[i * element_width +: element_width] ← temp_m[(i - 1) * element_width +: element_width]
    Qm[i * element_width +: element_width] ← temp_d[(i - 1) * element_width +: element_width]

Example

VTRN.dt q0, q2

Encoding

Binary Layout
111100111
31:23
D
22
11
21:20
size
19:18
10
17:16
Vd
15:12
0
11
0001
10:7
1
6
M
5
0
4
Vm
3:0
 
Format NEON 2-Reg
Opcode 0xF3B200C0
Extension NEON (SIMD)

Operands

  • Qd
    Dest/Src1
  • Qm
    Second source 128-bit SIMD register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B20080 VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm
0xF3B200C0 VTRN{<c>}{<q>}.<dt> <Qd>, <Qm> A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0001 | 1 | M | 0 | Vm
0xFFB20080 VTRN{<c>}{<q>}.<dt> <Dd>, <Dm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0001 | 0 | M | 0 | Vm
0xFFB200C0 VTRN{<c>}{<q>}.<dt> <Qd>, <Qm> T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0001 | 1 | M | 0 | Vm

Description

Vector Transpose treats the elements of its operand vectors as elements of 2 x 2 matrices, and transposes the matrices. The elements of the vectors can be 8-bit, 16-bit, or 32-bit. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    h = elements DIV 2;

    for r = 0 to regs-1
        if d == m then
            D[d+r] = bits(64) UNKNOWN;
        else
            for e = 0 to h-1
                Elem[D[d+r],2*e+1,esize] = Elem[Din[m+r],2*e,esize];
                Elem[D[m+r],2*e,esize] = Elem[Din[d+r],2*e+1,esize];