strexb
Store Register Exclusive Byte (A32)
STREXB<c> <Rd>, <Rt>, [<Rn>]
Stores a byte if address is still exclusive.
Details
Conditionally stores a byte to memory if the address is still marked as exclusive, returning a status in Rd (0=success, 1=failure). No condition flags are modified by the store result; success/failure is reported only in Rd. This is an A32-only instruction that atomically releases the exclusive lock and performs the write only if the lock is still held from a prior LDREXB.
Pseudocode Operation
if ConditionPassed(cond) then
address ← Rn
byte_value ← Rt[7:0]
if ExclusiveMonitorSet(address, 1) then
[address] ← byte_value
Rd ← 0
ClearExclusiveMonitor(address, 1)
else
Rd ← 1
Example
STREXB r0, r3, [r1]
Encoding
Binary Layout
cond
00011
10
0
Rn
Rd
1
1
1
1
1001
Rt
Operands
-
Rd
Status -
Rt
Transfer general-purpose register (load/store) -
Rn
First source / base general-purpose register
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x01C00F90 | STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] | A32 | cond | 00011 | 10 | 0 | Rn | Rd | 1 | 1 | 1 | 1 | 1001 | Rt | ||
| 0xE8C00F40 | STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>] | T32 | 11101000110 | 0 | Rn | Rt | 1111 | 01 | 00 | Rd |
Description
Store Register Exclusive Byte derives an address from a base register value, stores a byte from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.
For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
address = R[n];
if AArch32.ExclusiveMonitorsPass(address,1) then
MemA[address,1] = R[t]<7:0>;
R[d] = ZeroExtend('0', 32);
else
R[d] = ZeroExtend('1', 32);