sadd8

Signed Add 8 (A32)

SADD8<c> <Rd>, <Rn>, <Rm>

Parallel add of four signed 8-bit bytes.

Details

Performs four independent parallel signed 8-bit additions, one for each byte of Rn and Rm; results are stored in the corresponding bytes of Rd. The CPSR GE[3:0] flags are updated to reflect signed overflow in each byte; N, Z, C, V are unaffected. A32 only; requires DSP extension; executes in User and Privileged modes.

Pseudocode Operation

Rd[31:24] ← Rn[31:24] + Rm[31:24]
Rd[23:16] ← Rn[23:16] + Rm[23:16]
Rd[15:8] ← Rn[15:8] + Rm[15:8]
Rd[7:0] ← Rn[7:0] + Rm[7:0]
for i = 0 to 3:
  GE[i] ← (Rd[i*8+7:i*8] >= 0) ? 1 : 0

Example

SADD8 r0, r1, r2

Encoding

Binary Layout
cond
01100
001
Rn
Rd
1
1
1
1
1
00
1
Rm
 
Format SIMD Integer
Opcode 0x06100F90
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06100F90 SADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 001 | Rn | Rd | 1 | 1 | 1 | 1 | 1 | 00 | 1 | Rm
0xFA80F000 SADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 000 | Rn | 1111 | Rd | 0 | 0 | 0 | 0 | Rm

Description

Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets PSTATE.GE according to the results of the additions.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);
    sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);
    sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);
    sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);
    R[d]<7:0>   = sum1<7:0>;
    R[d]<15:8>  = sum2<7:0>;
    R[d]<23:16> = sum3<7:0>;
    R[d]<31:24> = sum4<7:0>;
    PSTATE.GE<0>  = if sum1 >= 0 then '1' else '0';
    PSTATE.GE<1>  = if sum2 >= 0 then '1' else '0';
    PSTATE.GE<2>  = if sum3 >= 0 then '1' else '0';
    PSTATE.GE<3>  = if sum4 >= 0 then '1' else '0';