smmul

Signed Most Significant Word Multiply

SMMUL{R}<c> <Rd>, <Rn>, <Rm>

Multiplies and returns the top 32-bits of the 64-bit result.

Pseudocode Operation

product ← SignedMul(Rn, Rm)
Rd ← (product[63:32])

Example

SMMUL r0, r1, r2

Encoding

Binary Layout

cond

31:28

01110

27:23

101

22:20

Rd

19:16

1111

15:12

Rm

11:8

00

7:6

0

5

1

4

Rn

3:0

 

Format Multiply

Opcode 0x0750F010

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  First source / base general-purpose register
• Rm
  Second source / offset general-purpose register

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x0750F010	SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 01110 | 101 | Rd | 1111 | Rm | 00 | 0 | 1 | Rn
0xFB50F000	SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110110 | 101 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm

Description

Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = SInt(R[n]) * SInt(R[m]);
    if round then result = result + 0x80000000;
    R[d] = result<63:32>;