vsub
Vector Subtract (VFP)
VSUB<c>.F32 <Sd>, <Sn>, <Sm>
Subtracts two floating-point values.
Details
Subtracts two single-precision floating-point values (Sn - Sm) and stores the result in Sd. This VFP instruction operates on 32-bit IEEE 754 single-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.
Pseudocode Operation
Sd ← Sn - Sm
FPSCR.NZCV ← FP_CC(result)Example
VSUB.F32 s0, s1, s2
Encoding
Binary Layout
cond
1110
0
D
11
Vn
Vd
10
10
N
1
M
0
Vm
Operands
-
Sd
Destination 32-bit floating-point register -
Sn
First source 32-bit floating-point register -
Sm
Second source 32-bit floating-point register
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF2200D00 | VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | A32 | 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm | ||
| 0xF2200D40 | VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | A32 | 1111001 | 0 | 0 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm | ||
| 0x0E300940 | VSUB{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm | ||
| 0x0E300A40 | VSUB{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm | ||
| 0x0E300B40 | VSUB{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm | ||
| 0xEF200D00 | VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | T32 | 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm | ||
| 0xEF200D40 | VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | T32 | 111 | 0 | 11110 | D | 1 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm | ||
| 0xEE300940 | VSUB{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 1 | M | 0 | Vm | ||
| 0xEE300A40 | VSUB{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 1 | M | 0 | Vm | ||
| 0xEE300B40 | VSUB{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 1 | M | 0 | Vm | ||
| 0xF3000800 | VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | A32 | 1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm | ||
| 0xF3000840 | VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | A32 | 1111001 | 1 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm | ||
| 0xFF000800 | VSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | T32 | 111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm | ||
| 0xFF000840 | VSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | T32 | 111 | 1 | 11110 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm |
Description
Vector Subtract (floating-point) subtracts the elements of one vector from the corresponding elements of another vector, and places the results in the destination vector.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
Elem[D[d+r],e,esize] = FPSub(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
StandardFPSCRValue());
else // VFP instruction
case esize of
when 16
S[d] = Zeros(16) : FPSub(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
when 32
S[d] = FPSub(S[n], S[m], FPSCR[]);
when 64
D[d] = FPSub(D[n], D[m], FPSCR[]);