fccmp

Floating-Point Conditional Compare (Scalar)

FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond>

Compares floats only if condition is met, else sets flags to immediate.

Pseudocode Operation

if ConditionHolds(cond) then
  result ← FPCompare(Vn, Vm)
  N ← result.N
  Z ← result.Z
  C ← result.C
  V ← result.V
else
  N ← nzcv[3]
  Z ← nzcv[2]
  C ← nzcv[1]
  V ← nzcv[0]

Example

FCCMP Dn, Dm, #nzcv, cond

Encoding

Binary Layout

0

31

0

30

0

29

11110

28:24

00

23:22

1

21

Rm

20:16

cond

15:12

01

11:10

Rn

9:5

0

4

nzcv

3:0

 

Format FP Compare

Opcode 0x1E200400

Extension Floating Point

Operands

• Hn|Sn|Dn
  First source SIMD&FP register (half, single or double-precision)
• Hm|Sm|Dm
  Second source SIMD&FP register (half, single or double-precision)
• nzcv
  Def Flags
• cond
  Condition

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x1EE00400	FCCMP <Hn>, <Hm>, #<nzcv>, <cond>		A64		0 | 0 | 0 | 11110 | 11 | 1 | Rm | cond | 01 | Rn | 0 | nzcv
0x1E200400	FCCMP <Sn>, <Sm>, #<nzcv>, <cond>		A64		0 | 0 | 0 | 11110 | 00 | 1 | Rm | cond | 01 | Rn | 0 | nzcv
0x1E600400	FCCMP <Dn>, <Dm>, #<nzcv>, <cond>		A64		0 | 0 | 0 | 11110 | 01 | 1 | Rm | cond | 01 | Rn | 0 | nzcv

Description

Floating-point Conditional quiet Compare (scalar). This instruction compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2;

operand2 = V[m, datasize];

if ConditionHolds(cond) then
    flags = FPCompare(operand1, operand2, FALSE, FPCR);
PSTATE.<N,Z,C,V> = flags;