vqrdmulh

Vector Saturating Rounding Doubling Multiply High

VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm>

Fixed-point multiply with rounding and saturation.

Details

Performs signed fixed-point saturating rounding doubling multiply on NEON vector elements, returning the high half with rounding. Each element in Qn is multiplied by the corresponding element in Qm, the result is doubled with rounding applied (via addition of 0x80000000 for 32-bit or 0x8000 for 16-bit before right-shift), saturated to the data type range, and the high half is written to Qd. The NEON condition flags are not affected; saturation is indicated via the FPSCR QC bit.

Pseudocode Operation

for i = 0 to elements_in_128bit(dt) - 1 do
  product ← (Qn[i] * Qm[i]) * 2
  if dt == S32 then
    product ← (product + 0x80000000) >> 32
  else
    product ← (product + 0x8000) >> 16
  Qd[i] ← SignedSaturate(product, dt)
FPSCR.QC ← FPSCR.QC OR (saturation occurred)

Example

VQRDMULH.dt q0, q1, q2

Encoding

Binary Layout
1111001
1
0
D
size
Vn
Vd
1011
N
1
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF3000B40
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3000B00 VQRDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1011 | N | 0 | M | 0 | Vm
0xF3000B40 VQRDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm
0xF2800D40 VQRDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]> A32 1111001 | 0 | 1 | D | size | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xF3800D40 VQRDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]> A32 1111001 | 1 | 1 | D | size | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xFF000B00 VQRDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1011 | N | 0 | M | 0 | Vm
0xFF000B40 VQRDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | size | Vn | Vd | 1011 | N | 1 | M | 0 | Vm
0xEF800D40 VQRDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]> T32 111 | 0 | 11111 | D | size | Vn | Vd | 1101 | N | 1 | M | 0 | Vm
0xFF800D40 VQRDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]> T32 111 | 1 | 11111 | D | size | Vn | Vd | 1101 | N | 1 | M | 0 | Vm

Description

Vector Saturating Rounding Doubling Multiply Returning High Half multiplies corresponding elements in two vectors, doubles the results, and places the most significant half of the final results in the destination vector. The results are rounded. For truncated results see VQDMULH. The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD scalars. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    round_const = 1 << (esize-1);
    integer op2;
    if scalar_form then op2 = SInt(Elem[D[m],index,esize]);
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = SInt(Elem[D[n+r],e,esize]);
            if !scalar_form then op2 = SInt(Elem[D[m+r],e,esize]);
            (result, sat) = SignedSatQ((2*op1*op2 + round_const) >> esize, esize);
            Elem[D[d+r],e,esize] = result;
            if sat then FPSCR.QC = '1';