shl

Vector Shift Left (Immediate)

SHL <Vd>.<T>, <Vn>.<T>, #<shift>

Shifts elements left by immediate value.

Pseudocode Operation

for i = 0 to elements_in_vector(Q, size) - 1 do
  if shift_amount < element_width(size) then
    Vd[i] ← Vn[i] << shift_amount
  else
    Vd[i] ← 0
  end if
end for

Example

SHL v0.4s.T, v1.4s.T, #LSL

Encoding

Binary Layout

011110

28:23

immh

22:19

immb

18:16

01010

15:11

9:5

4:0

Format SIMD Shift Imm

Opcode 0x0F005400

Extension NEON (SIMD)

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register
shift
Imm

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x5F405400	SHL D<d>, D<n>, #<shift>		A64		01 \| 0 \| 111110 \| immh \| immb \| 01010 \| 1 \| Rn \| Rd
0x0F005400	SHL <Vd>.<T>, <Vn>.<T>, #<shift>		A64		0 \| Q \| 0 \| 011110 \| immh \| immb \| 01010 \| 1 \| Rn \| Rd

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;

for e = 0 to elements-1
    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);

V[d, datasize] = result;

shl