eret
Exception Return (Thumb)
ERET
Returns from an exception (Thumb state).
Details
Exception Return: Returns from exception handling to the instruction following the exception. Restores the PC from ELR_ELx and PSTATE from SPSR_ELx. Execution state and privilege level are determined by the restored PSTATE. This instruction is only available in privileged modes (EL1 and above in AArch64, or with sufficient privilege in A32/T32).
Pseudocode Operation
PC ← ELR_ELx
PSTATE ← SPSR_ELx
ExecutionState ← PSTATE.SS
PrivilegeLevel ← PSTATE.M
Example
ERET
Encoding
Binary Layout
111100111101
1110
10
0
0
1
1
1
1
00000000
Operands
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0160006E | ERET{<c>}{<q>} | A32 | cond | 00010110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0110 | 1 | 1 | 1 | 0 | ||
| 0xF3DE8F00 | ERET{<c>}{<q>} | T32 | 111100111101 | 1110 | 10 | 0 | 0 | 1 | 1 | 1 | 1 | 00000000 |
Description
Exception Return.
The PE branches to the address held in the register holding the preferred return address, and restores PSTATE from SPSR_<current_mode>.
The register holding the preferred return address is:
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
Exception Return is constrained unpredictable in User mode and System mode.
In Debug state, the T1 encoding of ERET executes the DRPS operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
if !Halted() then
if PSTATE.M IN {M32_User,M32_System} then
UNPREDICTABLE; // UNDEFINED or NOP
else
new_pc_value = if PSTATE.EL == EL2 then ELR_hyp else R[14];
AArch32.ExceptionReturn(new_pc_value, SPSR[]);
else // Perform DRPS operation in Debug state
if PSTATE.M == M32_User then
UNDEFINED;
elsif PSTATE.M == M32_System then
UNPREDICTABLE; // UNDEFINED or NOP
else
SynchronizeContext();
DebugRestorePSR();