eon

Bitwise Exclusive OR NOT

EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

XORs register with NOT of shifted register (XNOR).

Details

Bitwise Exclusive OR NOT performs XNOR operation: destination = source1 XOR (NOT source2_shifted). The second source register can be shifted by immediate or register amount (LSL, LSR, ASR, ROR). The N and Z condition flags are set based on the result; C and V flags are unaffected. This 32-bit operation zero-extends the result in AArch64.

Pseudocode Operation

result ← Wn XOR (NOT (Wm << shift_amount))
Wd ← result[31:0]
N ← result[31]
Z ← (result == 0)

Example

EON w0, w1, w2

Encoding

Binary Layout
0
10
01010
shift
1
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x4A200000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x4A200000 EON <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 10 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0xCA200000 EON <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 10 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x05400000 EON <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 1 | 0000 | imm13 | Zdn

Description

Bitwise Exclusive-OR NOT (shifted register) performs a bitwise exclusive-OR NOT of a register value and an optionally-shifted register value, and writes the result to the destination register.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 EOR operand2;

X[d, datasize] = result;