ld1w

SVE Gather Load Words (Vector Index)

LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, SXTW #<shift>]

Loads words from non-contiguous addresses (Scatter-Gather).

Details

Performs a scatter-gather load of 32-bit words from non-contiguous memory addresses computed by adding scaled vector indices to a base address. Elements are loaded only where the corresponding predicate bit in Pg is set; inactive elements in Zt are zeroed. Does not modify condition flags. Execution restricted to AArch64 with SVE extension; may generate memory-access exceptions.

Pseudocode Operation

for i = 0 to VL/32-1
  if Pg[i] == 1
    addr ← Xn + (Zm[i] << shift)
    Zt[i, 32] ← [addr, 32]
  else
    Zt[i, 32] ← 0

Example

LD1W p0/m/Z, [x1, z2.s.S, SXTW #LSL]

Encoding

Binary Layout
100001010
xs
1
Zm
0
1
0
Pg
Rn
Zt
 
Format SVE Gather
Opcode 0x85204000
Extension SVE

Operands

  • Zt
    Transfer scalable vector register (SVE load/store)
  • Pg
    Mask
  • Xn
    First source / base 64-bit integer register
  • Zm
    Indices

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xA0404000 LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA040C000 LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000000100 | imm4 | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA0004000 LD1W { <Zt1>.S-<Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100000000 | Rm | 0 | 1 | 0 | PNg | Rn | Zt | 0
0xA000C000 LD1W { <Zt1>.S-<Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100000000 | Rm | 1 | 1 | 0 | PNg | Rn | Zt | 0 | 0
0xA1404000 LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA140C000 LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 101000010100 | imm4 | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0xA1004000 LD1W { <Zt1>.S, <Zt2>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100001000 | Rm | 0 | 1 | 0 | PNg | Rn | T | 0 | Zt
0xA100C000 LD1W { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <PNg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 10100001000 | Rm | 1 | 1 | 0 | PNg | Rn | T | 0 | 0 | Zt
0x8520C000 LD1W { <Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}] A64 1000010 | 1 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xC520C000 LD1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}] A64 1100010 | 1 | 0 | 01 | imm5 | 1 | 1 | 0 | Pg | Zn | Zt
0xA540A000 LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 101 | 0 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA560A000 LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 101 | 1 | 0 | imm4 | 101 | Pg | Rn | Zt
0xA5102000 LD1W { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}] A64 1010010 | 1 | 0 | 001 | imm4 | 001 | Pg | Rn | Zt
0xA5404000 LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2] A64 1010010 | 101 | 0 | Rm | 010 | Pg | Rn | Zt

Description

Gather load of unsigned words to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
bits(PL) mask = P[g, PL];
bits(VL) offset;
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
boolean contiguous = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = TRUE;
AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[] else X[n, 64];
    offset = Z[m, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned);
        bits(64) addr = GenerateAddress(base, off << scale, accdesc);
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);

Z[t, VL] = result;