fsqrt

Vector Floating-Point Square Root

FSQRT <Vd>.<T>, <Vn>.<T>

Calculates square root for each element.

Details

Calculates the floating-point square root of each element in the source vector and places the result in the destination vector. Floating-point exceptions (invalid operation, inexact) may be signaled per IEEE 754 semantics; no integer flags are affected. Available in 32-bit and 64-bit floating-point forms (sz controls element width) on AArch64 with NEON/ASIMD extension.

Pseudocode Operation

for i = 0 to elements_in_vector-1:
  element_size = 32 if sz==0 else 64
  Vd[element][element_size-1:0] = sqrt_fp(Vn[element][element_size-1:0])

Example

FSQRT v0.4s.T, v1.4s.T

Encoding

Binary Layout

011101

10000

11111

Format SIMD Two Register

Opcode 0x2EA1F800

Extension NEON (SIMD)

Operands

Vd
Destination SIMD/FP vector register
Vn
First source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x2EF9F800	FSQRT <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 01110 \| 1 \| 111100 \| 11111 \| 10 \| Rn \| Rd
0x2EA1F800	FSQRT <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 011101 \| sz \| 10000 \| 11111 \| 10 \| Rn \| Rd
0x1EE1C000	FSQRT <Hd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 10000 \| 11 \| 10000 \| Rn \| Rd
0x1E21C000	FSQRT <Sd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 10000 \| 11 \| 10000 \| Rn \| Rd
0x1E61C000	FSQRT <Dd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 10000 \| 11 \| 10000 \| Rn \| Rd
0x650DA000	FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	01100101 \| size \| 0011 \| 0 \| 1 \| 101 \| Pg \| Zn \| Zd

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];
bits(datasize) result;
bits(esize) element;

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPSqrt(element, FPCR);

V[d, datasize] = result;