vmul

Vector Multiply (VFP)

VMUL<c>.F32 <Sd>, <Sn>, <Sm>

Multiplies two floating-point values.

Details

Vector Multiply (VFP) performs single-precision floating-point multiplication of Sn and Sm, storing the result in Sd. The operation follows IEEE 754 semantics, updating the FPSCR exception flags (IXC, OFC, UFC, IOC, DZC) based on the result but not affecting the ARM condition flags N, Z, C, V. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Pseudocode Operation

Sd ← FP_Multiply(Sn, Sm)
FPSCR ← updated with floating-point exception flags

Example

VMUL.F32 s0, s1, s2

Encoding

Binary Layout
cond
1110
0
D
10
Vn
Vd
10
10
N
0
M
0
Vm
 
Format VFP Arith
Opcode 0x0E200A00
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sn
    First source 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3000D10 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xF3000D50 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0x0E200900 VMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E200A00 VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E200B00 VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xFF000D10 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xFF000D50 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0xEE200900 VMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE200A00 VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE200B00 VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xF2000910 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm
0xF2000950 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 1 | M | 1 | Vm
0xEF000910 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | op | 11110 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm
0xEF000950 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | op | 11110 | D | size | Vn | Vd | 1001 | N | 1 | M | 1 | Vm

Description

Vector Multiply multiplies corresponding elements in two vectors, and places the results in the destination vector. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then  // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                Elem[D[d+r],e,esize] = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
                                             StandardFPSCRValue());
    else             // VFP instruction
        case esize of
            when 16
                S[d] = Zeros(16) : FPMul(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
            when 32
                S[d] = FPMul(S[n], S[m], FPSCR[]);
            when 64
                D[d] = FPMul(D[n], D[m], FPSCR[]);