strh

Store Register Halfword (Register)

STRH <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores the low halfword of a register using register offset.

Details

Stores the low halfword (bits 15:0) of a 32-bit register to memory using register-based addressing with optional extension and shift of the offset register. Does not affect condition flags. AArch64-only; supports UXTW, UXTX, SXTW, SXTX extensions with optional left shift.

Pseudocode Operation

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[15:0]

Example

STRH w3, [x1, Rm ]

Encoding

Binary Layout
01
111
0
00
00
1
Rm
option
S
10
Rn
Rt
 
Format Load/Store
Opcode 0x78200800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • Rm
    Offset Reg

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x78000400 STRH <Wt>, [<Xn|SP>], #<simm> A64 01 | 111 | 0 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x78000C00 STRH <Wt>, [<Xn|SP>, #<simm>]! A64 01 | 111 | 0 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x79000000 STRH <Wt>, [<Xn|SP>{, #<pimm>}] A64 01 | 111 | 0 | 01 | 00 | imm12 | Rn | Rt
0x78200800 STRH <Wt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}] A64 01 | 111 | 0 | 00 | 00 | 1 | Rm | option | S | 10 | Rn | Rt

Description

Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a 32-bit register to the calculated address. For information about memory accesses, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.

Operation

bits(64) offset = ExtendReg(m, extend_type, shift, 64);
bits(64) address;
bits(16) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, TRUE);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, 16];
Mem[address, 2, accdesc] = data;