strd

Store Register Dual (Thumb)

STRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>]

Stores two words to memory (Thumb).

Details

Stores two consecutive 32-bit words from registers Rt and Rt2 to memory at the address computed from base register Rn with an optional immediate offset (scaled by 4). The instruction does not modify the condition flags. Execution in Thumb-2 state only.

Pseudocode Operation

address ← Rn + (imm8 << 2)
[address] ← Rt
[address + 4] ← Rt2

Example

STRD r3, r4, [r1, #+/-#16]

Encoding

Binary Layout
cond
000
1
U
1
1
0
Rn
Rt
imm4H
1
11
1
imm4L
 
Format Thumb Store
Opcode 0x016000F0
Extension A32 (Base)

Operands

  • Rt
    Transfer general-purpose register (load/store)
  • Rt2
    Second transfer register (load/store pair)
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x014000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}] A32 cond | 000 | 1 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0x004000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm> A32 cond | 000 | 0 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0x016000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]! A32 cond | 000 | 1 | U | 1 | 1 | 0 | Rn | Rt | imm4H | 1 | 11 | 1 | imm4L
0xE9400000 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}] T32 1110100 | 1 | U | 1 | 0 | 0 | Rn | Rt | Rt2 | imm8
0xE8600000 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm> T32 1110100 | 0 | U | 1 | 1 | 0 | Rn | Rt | Rt2 | imm8
0xE9600000 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]! T32 1110100 | 1 | U | 1 | 1 | 0 | Rn | Rt | Rt2 | imm8
0x010000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>] A32 cond | 000 | 1 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm
0x000000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], {+/-}<Rm> A32 cond | 000 | 0 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm
0x012000F0 STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]! A32 cond | 000 | 1 | U | 0 | 1 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 11 | 1 | Rm

Description

Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
    address = if index then offset_addr else R[n];
    if IsAligned(address, 8) then
        bits(64) data;
        if BigEndian(AccessType_GPR) then
            data<63:32> = R[t];
            data<31:0> = R[t2];
        else
            data<31:0> = R[t];
            data<63:32> = R[t2];
        MemA[address,8] = data;
    else
        MemA[address,4] = R[t];
        MemA[address+4,4] = R[t2];
    if wback then R[n] = offset_addr;