subs

Subtract and Set Flags (Shifted)

SUBS <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

Subtracts shifted register and updates flags.

Details

Subtracts the value in the second source register (optionally shifted) from the first source register and updates all condition flags. The shift can be LSL, LSR, ASR, or ROR by an amount specified in the immediate field. The N, Z, C, and V flags are set according to the result. This instruction executes in AArch64 state and requires no special privileges.

Pseudocode Operation

shift_amount ← imm6; shifted_Wm ← ApplyShift(Wm, shift_type, shift_amount); result ← Wn - shifted_Wm; Wd ← result; N ← result[31]; Z ← (result == 0); C ← BorrowFrom(Wn, shifted_Wm); V ← OverflowFrom(Wn, shifted_Wm, result)

Example

SUBS w0, w1, w2

Encoding

Binary Layout
0
1
1
01011
shift
0
Rm
imm6
Rn
Rd
 
Format Data Processing
Opcode 0x6B000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6B200000 SUBS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}} A64 0 | 1 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0xEB200000 SUBS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}} A64 1 | 1 | 1 | 01011 | 00 | 1 | Rm | option | imm3 | Rn | Rd
0x71000000 SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>} A64 0 | 1 | 1 | 100010 | sh | imm12 | Rn | Rd
0xF1000000 SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>} A64 1 | 1 | 1 | 100010 | sh | imm12 | Rn | Rd
0x6B000000 SUBS <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 1 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd
0xEB000000 SUBS <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 1 | 1 | 01011 | shift | 0 | Rm | imm6 | Rn | Rd

Description

Subtract (shifted register), setting flags, subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(4) nzcv;

operand2 = NOT(operand2);
(result, nzcv) = AddWithCarry(operand1, operand2, '1');

PSTATE.<N,Z,C,V> = nzcv;

X[d, datasize] = result;