bfi
Bit Field Insert (Thumb)
BFI <Rd>, <Rn>, #<lsb>, #<width>
Inserts a bitfield into a register.
Pseudocode Operation
msb ← lsb + width - 1
mask ← (1 << (msb + 1)) - (1 << lsb)
Rd ← (Rd AND NOT mask) OR ((Rn << lsb) AND mask)
Example
BFI r0, r1, #0, #width
Encoding
Binary Layout
11110
31:27
0
26
11
25:24
01
23:22
1
21
0
20
Rn
19:16
0
15
imm3
14:12
Rd
11:8
imm2
7:6
0
5
msb
4:0
Operands
-
Rd
Destination general-purpose register -
Rn
First source / base general-purpose register -
lsb
Start -
width
Width
Reference
View in Arm A64 ISA Reference ↗
Arm AArch32 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x07C00010 | BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> | A32 | cond | 0111110 | msb | Rd | lsb | 001 | Rn | ||
| 0xF3600000 | BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> | T32 | 11110 | 0 | 11 | 01 | 1 | 0 | Rn | 0 | imm3 | Rd | imm2 | 0 | msb |
Description
Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register.
Operation
if ConditionPassed() then
EncodingSpecificOperations();
R[d]<msbit:lsbit> = R[n]<(msbit-lsbit):0>;
// Other bits of R[d] are unchanged