bfi

Bit Field Insert (Thumb)

BFI <Rd>, <Rn>, #<lsb>, #<width>

Inserts a bitfield into a register.

Details

Inserts a bitfield from a source register into a destination register, clearing bits from lsb to lsb+width-1 and inserting the corresponding bits from Rn. No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6T2 and later.

Pseudocode Operation

msb ← lsb + width - 1
mask ← (1 << (msb + 1)) - (1 << lsb)
Rd ← (Rd AND NOT mask) OR ((Rn << lsb) AND mask)

Example

BFI r0, r1, #0, #width

Encoding

Binary Layout
11110
0
11
01
1
0
Rn
0
imm3
Rd
imm2
0
msb
 
Format Thumb Bitfield
Opcode 0xF3600000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • lsb
    Start
  • width
    Width

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x07C00010 BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> A32 cond | 0111110 | msb | Rd | lsb | 001 | Rn
0xF3600000 BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> T32 11110 | 0 | 11 | 01 | 1 | 0 | Rn | 0 | imm3 | Rd | imm2 | 0 | msb

Description

Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    R[d]<msbit:lsbit> = R[n]<(msbit-lsbit):0>;
    // Other bits of R[d] are unchanged