mls

Multiply Subtract (Thumb)

MLS <Rd>, <Rm>, <Ra>, <Rn>

Rd = Rn - (Rm * Ra).

Details

Multiply Rm by Ra and subtract the result from Rn, placing the 32-bit result in Rd. Condition flags N, Z, C, and V are not affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

Pseudocode Operation

Rd ← Rn - (Rm × Ra); result is 32-bit

Example

MLS r0, r2, r5, r1

Encoding

Binary Layout
111110110
000
Rn
Ra
Rd
00
01
Rm
 
Format Thumb Mul
Opcode 0xFB000010
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • Rm
    Second source / offset general-purpose register
  • Ra
    Accumulator general-purpose register (multiply-add)
  • Rn
    Acc

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x00600090 MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> A32 cond | 0000 | 011 | 0 | Rd | Ra | Rm | 1001 | Rn
0xFB000010 MLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra> T32 111110110 | 000 | Rn | Ra | Rd | 00 | 01 | Rm

Description

Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = SInt(R[n]);  // operand1 = UInt(R[n]) produces the same final results
    operand2 = SInt(R[m]);  // operand2 = UInt(R[m]) produces the same final results
    addend   = SInt(R[a]);  // addend   = UInt(R[a]) produces the same final results
    result = addend - operand1 * operand2;
    R[d] = result<31:0>;