sha512su1

SHA512 Schedule Update 1 (A32)

SHA512SU1.64 <Qd>, <Qn>, <Qm>

SHA512 schedule update instruction 1.

Details

Performs the second schedule update operation for SHA-512 message scheduling, combining Qd and Qn with Qm to compute the next message schedule value. This operation incorporates previous schedule elements and the second sigma transformation. This is an A32 Advanced SIMD instruction requiring the SHA512 Cryptographic Extension. Condition flags are not affected.

Pseudocode Operation

Qd ← SHA512_SU_1(Qd, Qn, Qm)

Example

SHA512SU1.64 q0, q1, q2

Encoding

Binary Layout
11001110011
Rm
1
0
00
10
Rn
Rd
 
Format Crypto 3-Reg
Opcode 0xCE608800
Extension Crypto (SHA512)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xCE608800 SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D A64 11001110011 | Rm | 1 | 0 | 00 | 10 | Rn | Rd

Description

SHA512 Schedule Update 1 takes the values from the three source SIMD&FP registers and produces a 128-bit output value that combines the gamma1 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register. This instruction is implemented only when FEAT_SHA512 is implemented.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(64) sig1;
bits(128) Vtmp;
bits(128) x = V[n, 128];
bits(128) y = V[m, 128];
bits(128) w = V[d, 128];

sig1 = ROR(x<127:64>, 19) EOR ROR(x<127:64>, 61) EOR ('000000':x<127:70>);
Vtmp<127:64> = w<127:64> + sig1 + y<127:64>;
sig1 = ROR(x<63:0>, 19) EOR ROR(x<63:0>, 61) EOR ('000000':x<63:6>);
Vtmp<63:0> = w<63:0> + sig1 + y<63:0>;
V[d, 128] = Vtmp;