rev

Reverse Bytes (Thumb)

REV <Rd>, <Rm>

Endian swap (Thumb).

Pseudocode Operation

Rd ← (Rm[7:0] << 24) | (Rm[15:8] << 16) | (Rm[23:16] << 8) | Rm[31:24]

Example

REV r0, r2

Encoding

Binary Layout

10111010

15:8

7:6

5:3

2:0

Format Thumb Data Proc

Opcode 0xBA00

Extension T32 (Thumb)

Operands

Rd
Destination general-purpose register
Rm
Second source / offset general-purpose register

Other forms of rev

rev SVE Reverse Vector, SVE
rev Reverse Bytes (64-bit), Base
rev Reverse Bytes (Thumb), A32 (Base)
rev Reverse Bytes (32-bit), Base
rev Reverse Bytes (A32), A32 (Base)

Across architectures

Byte Swap (Endianness Reversal) : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x06BF0F30	REV{<c>}{<q>} <Rd>, <Rm>	A32	cond \| 01101 \| 0 \| 11 \| 1 \| 1 \| 1 \| 1 \| Rd \| 1 \| 1 \| 1 \| 1 \| 0 \| 011 \| Rm
0xBA00	REV{<c>}{<q>} <Rd>, <Rm>	T32	10111010 \| 00 \| Rm \| Rd
0xFA90F080	REV{<c>}.W <Rd>, <Rm>	T32	111110101 \| 001 \| Rn \| 1111 \| Rd \| 10 \| 00 \| Rm

Description

Byte-Reverse Word reverses the byte order in a 32-bit register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    bits(32) result;
    result<31:24> = R[m]<7:0>;
    result<23:16> = R[m]<15:8>;
    result<15:8>  = R[m]<23:16>;
    result<7:0>   = R[m]<31:24>;
    R[d] = result;

rev