ror

Rotate Right (A32)

ROR{S}<c> <Rd>, <Rm>, <Rs>

Rotates register right.

Pseudocode Operation

shift_amount ← Rs[7:0] mod 32
if shift_amount == 0 then
  result ← Rm
  carry_out ← C
else
  result ← (Rm >> shift_amount) | (Rm << (32 - shift_amount))
  carry_out ← Rm[shift_amount - 1]
endif
Rd ← result
if S == 1 then
  N ← result[31]
  Z ← (result == 0)
  C ← carry_out
endif

Example

ROR r0, r2, r6

Encoding

Binary Layout

cond

31:28

00011

27:23

22:21

0000

19:16

15:12

11:8

6:5

3:0

Format Data Proc

Opcode 0x01A00070

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Rm
Second source / offset general-purpose register
Rs
Shift amount general-purpose register

Across architectures

Rotate Left : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x01A00060	ROR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| imm5 \| 11 \| 0 \| Rm
0xEA4F0030	ROR{<c>}{<q>} {<Rd>,} <Rm>, #<imm>	T32	1110101 \| 0010 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| 11 \| Rm
0x01A00070	ROR{<c>}{<q>} {<Rd>,} <Rm>, <Rs>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| Rs \| 0 \| 11 \| 1 \| Rm
0x41C0	ROR<c>{<q>} {<Rdm>,} <Rdm>, <Rs>	T32	010000 \| 0111 \| Rs \| Rdm
0xFA60F000	ROR<c>.W {<Rd>,} <Rm>, <Rs>	T32	111110100 \| 11 \| 0 \| Rm \| 1111 \| Rd \| 0000 \| Rs

Description

Provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register

ror