brkb

SVE Break Before First True

BRKB <Pd>.B, <Pg>/Z, <Pn>.B

Sets predicates up to (but excluding) the first active element.

Details

SVE Break Before First True sets all predicate elements up to (but excluding) the first active element in Pn (as governed by Pg) to 1, and all subsequent elements to 0. The instruction is used to isolate processing before the first true element in a predicate. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

Pseudocode Operation

integer esize = 8;
integer elements = VL / esize;
integer g = 0;
for e = 0 to elements-1
  if Pg[e] == '1' and Pn[e] == '1' and g == 0 then
    g = 1;
  if g == 0 then
    Pd[e] = '1';
  else
    Pd[e] = '0';

Example

BRKB p0.B, p0/m/Z, p1.B

Encoding

Binary Layout
00100101
1
0
01000001
Pg
0
Pn
M
Pd
 
Format SVE Predicate
Opcode 0x25904000
Extension SVE

Operands

  • Pd
    Destination predicate register (SVE)
  • Pg
    Limit
  • Pn
    First source predicate register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x25904000 BRKB <Pd>.B, <Pg>/<ZM>, <Pn>.B A64 00100101 | 1 | 0 | 01000001 | Pg | 0 | Pn | M | Pd

Description

Sets destination predicate elements up to but not including the first active and true source element to true, then sets subsequent elements to false. Inactive elements in the destination predicate register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected. Does not set the condition flags.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(PL) operand  = P[n, PL];
bits(PL) operand2 = P[d, PL];
boolean break = FALSE;
bits(PL) result;
constant integer psize = esize DIV 8;

for e = 0 to elements-1
    boolean element = ActivePredicateElement(operand, e, esize);
    if ActivePredicateElement(mask, e, esize) then
        break = break || element;
        bit pbit = if !break then '1' else '0';
        Elem[result, e, psize] = ZeroExtend(pbit, psize);
    elsif merging then
        bit pbit = PredicateElement(operand2, e, esize);
        Elem[result, e, psize] = ZeroExtend(pbit, psize);
    else
        Elem[result, e, psize] = ZeroExtend('0', psize);

if setflags then
    PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;