fsqrt

SVE Floating-Point Square Root

FSQRT <Zdn>.<T>, <Pg>/M, <Zdn>.<T>

Calculates square root of floats.

Pseudocode Operation

for i = 0 to VL-1
  if Pg[i] == '1' then
    Zdn[i] ← FPSquareRoot(Zdn[i])
  // else Zdn[i] unchanged
// FP exception flags updated per IEEE 754

Example

FSQRT z0.s.T, p0/m/M, z0.s.T

Encoding

Binary Layout

01100101

31:24

size

23:22

0011

21:18

0

17

1

16

101

15:13

Pg

12:10

Zn

9:5

Zd

4:0

 

Format SVE FP Unary

Opcode 0x650DA000

Extension SVE

Operands

• Zdn
  Combined destination/source scalable vector register (SVE)
• Pg
  Mask

Related

Other forms of fsqrt

• fsqrt Floating-Point Square Root (Scalar)
• fsqrt Vector Floating-Point Square Root
• fsqrt Floating-Point Square Root (Half-Precision)

Across architectures

Floating-Point Square Root : how x86, ARM, RISC-V, and PowerISA each do this.

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2EF9F800	FSQRT <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 01110 | 1 | 111100 | 11111 | 10 | Rn | Rd
0x2EA1F800	FSQRT <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 011101 | sz | 10000 | 11111 | 10 | Rn | Rd
0x1EE1C000	FSQRT <Hd>, <Hn>		A64		0 | 0 | 0 | 11110 | 11 | 10000 | 11 | 10000 | Rn | Rd
0x1E21C000	FSQRT <Sd>, <Sn>		A64		0 | 0 | 0 | 11110 | 00 | 10000 | 11 | 10000 | Rn | Rd
0x1E61C000	FSQRT <Dd>, <Dn>		A64		0 | 0 | 0 | 11110 | 01 | 10000 | 11 | 10000 | Rn | Rd
0x650DA000	FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T>		A64		01100101 | size | 0011 | 0 | 1 | 101 | Pg | Zn | Zd

Description

Calculate the square root of each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = FPSqrt(element, FPCR);

Z[d, VL] = result;