index

SVE Create Index Vector

INDEX <Zd>.<T>, <Start>, <Step>

Generates a vector of indices: V[i] = Start + i * Step.

Pseudocode Operation

for i = 0 to VL/esize-1
  Zd[i] ← Start + (i * Step)

Example

INDEX z0.s.T, Start, Step

Encoding

Binary Layout

00000100

31:24

size

23:22

1

21

Rm

20:16

010011

15:10

Rn

9:5

Zd

4:0

 

Format SVE Index

Opcode 0x04204C00

Extension SVE

Operands

• Zd
  Destination scalable vector register (SVE)
• Start
  Scalar/Imm
• Step
  Scalar/Imm

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04204000	INDEX <Zd>.<T>, #<imm1>, #<imm2>		A64		00000100 | size | 1 | imm5b | 010000 | imm5 | Zd
0x04204800	INDEX <Zd>.<T>, #<imm>, <R><m>		A64		00000100 | size | 1 | Rm | 010010 | imm5 | Zd
0x04204400	INDEX <Zd>.<T>, <R><n>, #<imm>		A64		00000100 | size | 1 | imm5 | 010001 | Rn | Zd
0x04204C00	INDEX <Zd>.<T>, <R><n>, <R><m>		A64		00000100 | size | 1 | Rm | 010011 | Rn | Zd

Description

Populates the destination vector by setting the first element to the first signed scalar integer operand and monotonically incrementing the value by the second signed scalar integer operand for each subsequent element. The scalar source operands are general-purpose registers in which only the least significant bits corresponding to the vector element size are used and any remaining bits are ignored. This instruction is unpredicated.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(esize) operand1 = X[n, esize];
integer element1 = SInt(operand1);
bits(esize) operand2 = X[m, esize];
integer element2 = SInt(operand2);
bits(VL) result;

for e = 0 to elements-1
    integer index = element1 + e * element2;
    Elem[result, e, esize] = index<esize-1:0>;

Z[d, VL] = result;