fscale
FSCALE <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
Floating-point Scale.
Pseudocode Operation
No pseudocode available.
Encoding
Binary Layout
01100101
31:24
size
23:22
00
21:20
100
19:17
1
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
Related
More in SVE
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x2EC03C00 | FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | 1 | 10 | Rm | 00 | 111 | 1 | Rn | Rd | ||
| 0x2EA0FC00 | FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 1 | 01110 | size | 1 | Rm | 11111 | 1 | Rn | Rd | ||
| 0xC120A180 | FSCALE { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101000 | 01100 | Zdn | 0 | ||
| 0xC120A980 | FSCALE { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> | A64 | 11000001 | size | 10 | Zm | 101010 | 01100 | Zdn | 0 | 0 | ||
| 0xC120B180 | FSCALE { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } | A64 | 11000001 | size | 1 | Zm | 0101100 | 011 | 0 | 0 | Zdn | 0 | ||
| 0xC120B980 | FSCALE { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } | A64 | 11000001 | size | 1 | Zm | 00101110 | 011 | 0 | 0 | Zdn | 0 | 0 | ||
| 0x65098000 | FSCALE <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | A64 | 01100101 | size | 00 | 100 | 1 | 100 | Pg | Zm | Zdn |
Description
Multiply the active floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.
Operation
CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;
for e = 0 to elements-1
bits(esize) element1 = Elem[operand1, e, esize];
if ActivePredicateElement(mask, e, esize) then
integer element2 = SInt(Elem[operand2, e, esize]);
Elem[result, e, esize] = FPScale(element1, element2, FPCR);
else
Elem[result, e, esize] = element1;
Z[dn, VL] = result;