fmaxv

SVE Floating-Point Maximum Reduction

FMAXV <Vd>, <Pg>, <Zn>.<T>

Finds max float in vector.

Pseudocode Operation

bits(esize) result = NegInfinity(esize);
for i = 0 to VL/esize - 1
  if Pg[i] == '1' then
    element = Zn[i*esize +: esize];
    if element > result (FP) || IsNaN(result) then result = element;
Vd[0 +: esize] ← result;

Example

FMAXV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout
01100101
31:24
size
23:22
000
21:19
11
18:17
0
16
001
15:13
Pg
12:10
Zn
9:5
Vd
4:0
 
Format SVE Reduction
Opcode 0x65062000
Extension SVE

Operands

  • Vd
    Dest Scalar
  • Pg
    Mask
  • Zn
    Vector

Related

Other forms of fmaxv

  • fmaxv Floating-Point Maximum Reduction (NEON)

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E30F800 FMAXV <V><d>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 0 | 011000 | 01111 | 10 | Rn | Rd
0x6E30F800 FMAXV S<d>, <Vn>.4S A64 0 | 1 | 1 | 01110 | 0 | 0 | 11000 | 01111 | 10 | Rn | Rd
0x65062000 FMAXV <V><d>, <Pg>, <Zn>.<T> A64 01100101 | size | 000 | 11 | 0 | 001 | Pg | Zn | Vd

Description

Floating-point maximum horizontally over all lanes of a vector using a recursive pairwise reduction, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as -Infinity. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows:

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) identity = FPInfinity('1', esize);

V[d, esize] = FPReducePredicated(ReduceOp_FMAX, operand, mask, identity, FPCR);