vsri

Vector Shift Right and Insert

VSRI<c>.<size> <Qd>, <Qm>, #<imm>

Shifts bits right and inserts into destination.

Details

Shifts each element in the source register right by the immediate shift amount and inserts the shifted bits into the high bits of the destination element, leaving the low bits of the destination unchanged (merging operation). The shift amount is unsigned. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← imm6
  shifted ← Qm[i] >> shift_amount
  mask ← ((1 << (element_size - shift_amount)) - 1) << shift_amount
  Qd[i] ← (Qd[i] & ~mask) | (shifted & mask)
endfor

Example

VSRI.size q0, q2, #16

Encoding

Binary Layout
1111001
1
1
D
imm6
Vd
0100
L
1
M
1
Vm
 
Format NEON Shift
Opcode 0xF3800450
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3800410 VSRI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm> A32 1111001 | 1 | 1 | D | imm6 | Vd | 0100 | L | 0 | M | 1 | Vm
0xF3800450 VSRI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm> A32 1111001 | 1 | 1 | D | imm6 | Vd | 0100 | L | 1 | M | 1 | Vm
0xFF800410 VSRI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm> T32 111 | 1 | 11111 | D | imm6 | Vd | 0100 | L | 0 | M | 1 | Vm
0xFF800450 VSRI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm> T32 111 | 1 | 11111 | D | imm6 | Vd | 0100 | L | 1 | M | 1 | Vm

Description

Vector Shift Right and Insert takes each element in the operand vector, right shifts them by an immediate value, and inserts the results in the destination vector. Bits shifted out of the right of each element are lost. The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between data types. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    mask = LSR(Ones(esize), shift_amount);
    for r = 0 to regs-1
        for e = 0 to elements-1
            shifted_op = LSR(Elem[D[m+r],e,esize], shift_amount);
            Elem[D[d+r],e,esize] = (Elem[D[d+r],e,esize] AND NOT(mask)) OR shifted_op;